DS3106LN+【PDF 4/92 页】IC TIMING LINE CARD 64-LQFP

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Sheet目录1994

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DS3106

PIN NAME

(1)

TYPE

(2)

PIN DESCRIPTION

SONSDH/

GPIO4

IOPD

SONET/SDH Frequency Select Input/General-Purpose I/O 4. When

RST goes high the state

of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS, and MCR6:DIG2SS.

After

RST goes high, this pin can be used as a general-purpose I/O pin. GPCR:GPIO4D

configures this pin as an input or an output. GPCR:GPIO4O specifies the output value.

GPSR:GPIO4 indicates the state of the pin.

Reset latched values:

0 = SDH rates (N x 2.048MHz)

1 = SONET rates (N x 1.544MHz)

INTREQ/LOS

Interrupt Request/Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit

determines whether the pin indicates interrupt requests or loss of signal (i.e., loss of selected

reference).

INTCR:LOS = 0: INTREQ mode

The behavior of this pin is configured in the INTCR register. Polarity can be active high or

active low. Drive action can be push-pull or open drain. The pin can also be configured as

a general-purpose output if the interrupt request function is not needed.

INTCR:LOS = 1: LOS mode

This pin indicates the real-time state of the selected reference activity monitor (see Section

7.5.3).

Table 6-4. SPI Bus Mode Pin Descriptions

See Section 7.9 for functional description and Section 10.4 for timing specifications.

PIN NAME

(1)

TYPE

(2)

PIN DESCRIPTION

IPU

Chip Select. This pin must be asserted (low) to read or write internal registers.

SCLK

Serial Clock. SCLK is always driven by the SPI bus master.

SDI

Serial Data Input. The SPI bus master transmits data to the device on this pin.

SDO

Serial Data Output. The device transmits data to the SPI bus master on this pin.

CPHA

Clock Phase. See Figure 7-4.

0 = Data is latched on the leading edge of the SCLK pulse.

1 = Data is latched on the trailing edge of the SCLK pulse.

Table 6-5. JTAG Interface Pin Descriptions

See Section 9 for functional description and Section 10.5 for timing specifications.

PIN NAME

(1)

TYPE

(2)

PIN DESCRIPTION

JTRST

IPU

JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If

not used,

JTRST can be held low or high.

JTCLK

JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If

not used, JTCLK can be held low or high.

JTDI

IPU

JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge

of JTCLK. If not used, JTDI can be held low or high.

JTDO

JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling

edge of JTCLK. If not used, leave unconnected.

JTMS

IPU

JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port

into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave

unconnected.

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